The present invention relates generally to memory circuits, and more particularly, to a read and write assist circuit for a static random access memory (SRAM) cell.
A semiconductor memory circuit stores data electronically. One type of memory circuit is a SRAM, which is made up of an array of SRAM cells. The SRAM cells retain data in a static form. An SRAM cell typically includes pull-up and pull-down transistors, pass-gate transistors, bit lines, and a word line. Threshold voltages of the pull-up, pull-down, and pass-gate transistors determine a static noise margin (SNM) and a write margin (i.e. stability of read and write operations, respectively) of the SRAM cell. However, as semiconductor device sizes shrink, fluctuations in the threshold voltages increase due to random dopant fluctuation (RDF), line edge roughness (LER), and short channel effects (SCE). These fluctuations in the threshold voltages result in fluctuations in the drive strengths of the transistors, which degrades the SNM and the write margin.
A conventional approach to reduce the degradation of the SNM and the write margin is to use a read and write assist circuit. A read assist circuit ensures an adequate SNM by decreasing the drive strengths of the pass-gate transistors or increasing the drive strengths of the pull-up transistors. On the other hand, a write assist circuit ensures an adequate write margin by increasing the drive strengths of the pass-gate transistors or decreasing the drive strengths of the pull-up transistors. These conflicting drive-strength requirements make it difficult to achieve both an adequate SNM and an adequate write margin at the same time. Further, the read assist technique degrades the read current of the SRAM cell, which affects its speed, whereas the write assist technique increases power consumption.
The SNM and the write margin of the SRAM cell are further dependent on temperature. The SNM degrades at high temperatures, while the write margin degrades at low temperatures. Thus, an improvement in the SNM results in degradation in the write margin, and vice-versa.
The read and write assist circuits may use biasing techniques along with the read and write assist techniques. The biasing techniques include generating a bias voltage that is provided to body terminals of the transistors in the SRAM cells. The biasing techniques may be implemented with biasing circuits that include various combinations of transistors, resistors, diodes, and the like. However, employing the biasing circuits consumes additional area and power.
Therefore, it would be advantageous to have a read and write assist circuit for an SRAM cell that maintains an SNM and a write margin above an acceptable level over a temperature range and increases the operational speed of the SRAM cell.